Digital transceivers use digital-to-analog converters (DACs) to convert modulated digital signals to corresponding analogs for transmission. Ideally, the frequency response of the analog signal includes information exclusive to the transmission band. However, in implementation, frequency spurs are generated in the bands adjacent to the transmission band, referred to as the receiving bands. These frequency spurs are in part an undesirable artifact of the digital-to-analog conversion process, and are therefore referred to as DAC images. The frequency at which the frequency spurs occur is determined by the sampling rate of the DAC.
One conventional method for removing, or minimizing the frequency spurs in the receiving bands is to double the sampling rate. Increasing the sampling rate is referred to as up-sampling. If frequency spurs are generated in the receiving bands when the DAC uses a first sampling rate, then doubling the sampling rate essentially moves the frequency spurs from the receiving band to the next adjacent band. Although doubling the sampling rate is effective in minimizing the frequency spurs in the receiving band, doubling the sampling rate requires a significant increase in power. For a portable device, such as a cellular telephone, this increased power shortens battery life.
Up-sampling is typically performed according to an up-sampling factor. The up-sampling factor can be an integer, denoted for example by M, as in the case of doubling the sampling rate, M=2, or the up-sampling factor can be a fraction greater than unity, such as M/N. Conventionally, fractional up-sampling is performed by first up-sampling by a factor of M, and then down-sampling by a factor of N. A fraction up-sampling filter is typically used to execute the fractional up-sampling. Using a typical fractional up-sampling filter, digital data at a lower clock rate is first up-sampled to a common multiple higher clock rate by injecting zeroes in the data stream. The result is then passed through a digital low-pass filter to remove higher frequency components induced by the injection of zeroes. Finally, a decimation of the resultant data stream is performed to obtain the desired data rate according to the up-sampling factor.
FIG. 1 illustrates a block diagram of a conventional fractional up-sampling filter. Digital data previously sampled at a first sample rate is up-sampled by an up-sampling filter 14. The up-sampling filter 14 up-samples the digital data by a factor of M, executed according to the clock rate of the clock 10. Digital data up-sampled by a factor of M is output from the up-sampling filter 14. This up-sampled digital data is passed to a down-sampling filter 18 via an anti-aliasing filter 16. The anti-aliasing filter 16 prevents aliasing, a form of distortion, in the conversion of the digital data samples back to a continuous analog signal. The down-sampling filter 18 down-samples the up-sampled digital data by a factor of N, executed according to the clock rate of the clock 12. This results in digital data up-sampled by a fractional up-sampling factor of M/N. The down-sampling filter 18 outputs the fractionally up-sampled digital data.
A significant drawback of the conventional fractional up-sampling filter is that the first up-sampling stage requires a relatively high clock rate. The process of up-sampling all of the digital data at the high clock rate, only to subsequently down-sample the up-sampled data is extremely inefficient, and also introduces spurious effects into the data. Power consumption is also a concern since more circuitry will be operated at a higher clock rate.